In earlier data processing systems, the Central Processing Unit (CPU) directly controlled the peripheral devices in the system. These systems employed a general purpose CPU for data processing functions, this CPU also controlled different types of peripherals. Such an implementation was not very efficient because a CPU is generally designed to be an efficient data processor and is not very suitable for peripheral control functions. The control function requirements of different peripheral devices attached to a system are too varied to permit efficient control using a general purpose CPU. Also, these control functions were performed using software instructions and hence were slow.
The next generation of systems utilized a peripheral controller as an interface between the CPU and the peripheral device that was to be controlled. In these systems, peripheral controllers were mostly designed to standardize the physical interface of the peripheral as viewed by the CPU, however, all intelligence required to operate the peripheral still resided in the CPU control programs.
In subsequent systems, more and more of the intelligence required to control the peripheral device was designed into the peripheral controller.
What is meant by intelligence in the context of this application is that the majority of decisions concerning the operation of the device are performed by the peripheral controller. These peripheral controllers were specialized in that a peripheral controller was designed to control one type of peripheral device, e.g. a disk controller was designed to control a disk drive, a printer controller was designed to control a printer, etc.
Since the peripheral controller was specialized, it could be designed to control the associated peripheral device much more efficiently. Also, many of the peripheral control functions could be implemented in the peripheral controller using hardware logic resulting in faster operation as compared to slower software control programs. This also permitted the CPU to perform data processing functions faster.
To more particularly explain the problems associated with known systems, reference will now be made to a typical data processing system. Such a system comprises a CPU with an associated peripheral controller coupled to the CPU. Coupled to the controller is a peripheral device such as an optical disk, magnetic disk, or the like.
Before explaining the typical sequence of operations, a disk subsystem is explained here. Disks store data on a physical media comprising of one or more storage surfaces, each surface is divided into tracks, these tracks are further divided into entities called sectors where blocks of data can be stored. Each sector consists of two major components, a header portion that identifies a sector uniquely; and a data portion, where a block of data can be stored.
The header portion typically consists of a surface number and a track number on which the sector is located, and a unique sector number assigned to it. An error detecting check code is usually appended to this header information to ensure that the header information recovered from the disk during the read operation is correct.
The data portion of the sector consists of a block of data. Typical block sizes of a sector are 256, 512, or 1024 bytes, although other sizes can also be implemented. Also, the data block size in a given disk is the same, although it can be varied from sector to sector. Usually, a check code, which can be error detecting or error detecting and correcting in nature, is appended to the block of data as it is written to the disk.
This check code is used by the peripheral controller to determine if an error occurred in the block of data during retrieval of data. If the check code is error detecting and correcting, the erroneously recovered data can be corrected by means of some error correcting mechanism. Data blocks can be read or written in integral multiple of sectors.
In a first known operating procedure, the peripheral controller can operate on one sector for each command. Normally, the peripheral controller is in an idle state and the CPU issues a command, for example, a READ ONE SECTOR command to the peripheral controller. Along with that command, the CPU will also provide the controller with command parameters, e.g. the surface, the track and the sector number of the sector to be read. Thereafter, the controller enters a busy state where it performs the read function specified by the CPU.
It begins by searching for the specified sector, and when and if the specified sector is found, the data from this sector is retrieved by the CPU using programmed input/output sequence. The peripheral controller then prepares a status code for the CPU in its status register and sends a signal to the CPU that the specified function has been completed. After this, the peripheral controller enters the idle state again and the status can be retrieved by the CPU.
In this type of procedure, since the CPU retrieves the status information only when the peripheral controller is idle, there is no chance of any contention between the CPU and the peripheral controller. What is meant by contention is that there is no chance that the CPU will read the status information from the peripheral controller at the same time that the peripheral controller is attempting to write it.
However, as more complex systems developed, this operating procedure became inadequate. More particularly, it became important that the peripheral controller should be able to perform multiple sector operations without assistance from the CPU. It must be able to perform error detection and correction operations without assistance from the CPU. It must also be able to perform data transfer operations without assistance from the CPU.
To maximize the overall throughput of the systems, many of these tasks must be performed at the same time. For example, while a previously read error-free sector data is being transferred, a correction operation can proceed on a sector of data that was recovered with error, and a new sector of data can be retrieved from the disk at the same time.
In other words, the system must be able to perform various tasks simultaneously. It is also important that the controller provide status information on a regular basis to the CPU to allow the CPU to adequately monitor the operation of the peripheral controller.
As an alternative to the above mentioned operating procedure, procedures are known in which the peripheral controller commands can be chained. In such procedures, a significant area is provided in the memory of the CPU such that the status of each of there commands can be placed in the memory as the peripheral controller operation proceeds.
In such a system, the CPU issues a chain of commands which will cause multiple events to happen in the peripheral controller. As the status information is generated after each event, this status is loaded into the pre-designated area of the memory where it can be examined by the CPU. This alternative procedure takes care of the contention problem outlined above, however, it requires a more complex CPU bus structure such as a multi-master CPU bus. It also requires large amount of memory to be set aside for status information.
In many systems, it is best to design the peripheral controller to perform as many complex functions as possible and keep the CPU functions as simple as possible. This allows very cheap CPU devices to be used in the peripheral subsystem and results in a more cost-effective solution. The two major requirements of the second operating procedure outlined above--more complex CPU and large amount of memory--are in direct opposition to the desirable characteristics of the cost-effective solution.
Accordingly, what is needed is a system that includes a CPU, a peripheral controller and a peripheral device in which contention problems are minimized. It is also important that the system be one in which the CPU is a relatively inexpensive part of the overall system. It is also important that the system be one in which the peripheral controller does not corrupt any status information generated during its operation. Accordingly, the present invention provides a system which overcomes the above-mentioned problems.